In continuation of a successful series of events, the 4th symposium of the Many-core Applications Research Community (MARC) will take place at the Hasso Plattner Institute for Software Systems Engineering in Potsdam. On December 8th and 9th, researchers from different fields will present their current and future work on many-core hardware architectures, their programming models, and the resulting research questions for the upcoming generation of heterogeneus parallel systems.
Both MARC members and interested external organizations are invited to submit unpublished reports, both on work in process or new results regarding software for novel many-core hardware architectures. While the Intel Single Chip Cloud Computer (SCC) serves as common research platform for most MARC members, other interesting research on next generation many-core platforms is also relevant for this event.
Topics of interest include, but are not limited to:
* Operating system support for novel many-core architectures
* Virtualization solutions to deal with hardware limitations
* Dealing with legacy software on novel many-core architectures
* New approaches for leveraging on-die messaging facilities
* Traditional and new programming models for novel many-core hardware
All authors are invited to submit original and unpublished work as either regular papers (maximum 6 pages) for oral presentation or short papers (maximum 4 pages) for poster presentation. Papers describing work-in-progress are also welcome.
| Welcome Speech | 00:13:38 | |
|---|---|---|
| Introduction by Prof. Polze | 00:06:57 | |
| Operating Systems and Middleware | 00:06:41 |
| Many Core Processors at Intel: Lessons Learned and Future Work | 00:47:20 | |
|---|---|---|
| Introduction | 00:11:21 | |
| SCC's MPB was big enough... | 00:08:16 | |
| Application level power management | 00:13:27 | |
| So how many cores? | 00:14:16 |
| Performance modeling for power consumption reduction on SCC | 00:21:45 | |
|---|---|---|
| Agenda and background | 00:09:22 | |
| Evaluation | 00:04:26 | |
| Case study | 00:07:57 |
| Parallel AI Planning on the SCC | 00:30:08 | |
|---|---|---|
| Motivations | 00:09:07 | |
| YAHSP2 in a few words | 00:08:36 | |
| Algorithms compared | 00:12:25 |
| Performance and power analysis of RCCE message passing on the SCC | 00:26:48 | |
|---|---|---|
| Manycore challenges | 00:09:18 | |
| Power measurements | 00:06:43 | |
| Experimenal setup | 00:10:47 |
| Ruby on SCC: Casually programming SCC with Ruby | 00:19:44 | |
|---|---|---|
| Our objective | 00:06:11 | |
| Ruby binding of RCCE | 00:04:37 | |
| Distributed objects with Ruby on SCC | 00:08:56 |
| Characterization and analysis of pipelined applications on the Intel SCC | 00:20:30 | |
|---|---|---|
| Why pipelining? | 00:04:35 | |
| The pipeline | 00:12:10 | |
| Deployment | 00:03:45 |
| Deterministic Execution on Many-Core platform | 00:35:38 | |
|---|---|---|
| Critical embedded systems | 00:07:50 | |
| Multi-core issues for deterministic execution | 00:06:39 | |
| FAS example | 00:10:55 | |
| SWCTT: Basic needs | 00:10:14 |
| Multicore-Experiments comparing SCC with other platforms | 00:31:22 | |
|---|---|---|
| LINO | 00:08:45 | |
| The Problem | 00:07:03 | |
| Results | 00:15:34 |
| Porting Android to SCC | 00:36:21 | |
|---|---|---|
| Things to know about Android | 00:12:04 | |
| sccLinux kernel | 00:13:15 | |
| Customized filesystem | 00:11:02 |
| Flexible sharing and replication mechanisms | 00:17:41 | |
|---|---|---|
| How to make SCC's shared memory usable? | 00:06:12 | |
| Cache and replica control on the SCC | 00:05:28 | |
| Tools: Control and Storage Container | 00:06:01 |
| Improved SCCMPB Channel: Scaling and Dynamic Processes Support | 00:20:43 | |
|---|---|---|
| Introduction | 00:08:15 | |
| MPB Partitions | 00:06:49 | |
| Channel Performance | 00:05:39 |
| Towards symmetric multi-processing support for operating systems on the Intel SCC | 00:27:34 | |
|---|---|---|
| Demo & Problem statement | 00:11:42 | |
| Memory | 00:12:25 | |
| SMP simulation in the RockyVisor | 00:03:27 |
| The path to MetalSVM: Shared virtual memory for the SCC | 00:18:46 | |
|---|---|---|
| Introduction | 00:03:22 | |
| SVM subsystem | 00:09:28 | |
| TCP/IP communication | 00:05:56 |
| Fiasco on the SCC | 00:18:47 | |
|---|---|---|
| FIASCO/L4RE | 00:02:48 | |
| Porting FIASCO | 00:09:27 | |
| Lesson learned | 00:06:32 |
